The present invention relates generally to a communication network, and, more particularly, to a communication system in a communication network for transmitting and receiving control frames in a manner that makes efficient usage of device pins.
A communication network includes multiple communication terminals such as user equipment (UEs), base stations, modems, and routers that communicate with each other over an air interface. Examples of UEs include hand-held devices such as cell phones, tablets, personal digital assistants (PDAs), and laptops with mobile broadband adapters. Each communication terminal includes a radio frequency integrated circuit (RFIC) connected to an antenna for transmitting and receiving communication data to and from another communication terminal/node. The RFIC includes a processor, peripheral circuits, and an interface. Examples of the interface include common public radio interface (CPRI) and a Joint Electron Devices Engineering Council (JEDEC) Standards Document (JESD) 204B-compliant serial interface. Examples of the peripheral circuits include a digital-to-analog converter (DAC), an analog-to-digital converter (ADC), a power amplifier, a low-noise amplifier (LNA) and the like.
The processor is connected to the peripheral circuits via the interface using general purpose input/output (GPIO) pins. The processor generates control data for the operation of the peripheral circuits. The control data includes an interrupt, a communication data status bit, clock data corresponding to a clock signal, voltage-mode select data corresponding to a voltage-mode select signal, an enable bit corresponding to an enable signal, and the like. For example, an ADC connected to at least one of the GPIO pins receives first control data via the GPIO pin. Similarly, a DAC connected to one of the GPIO pins receives second control data via the GPIO pin. However, the processor uses a significant number of GPIO pins to transmit the control data to the peripheral circuits, which limits the number of GPIO pins available to connect additional peripheral circuits to the processor. Thus, it is important to minimize the number of GPIO pins required to connect the processor to the RFIC.
Further, the RFIC consumes a lot of power in transmitting and receiving the communication data. Various communication standards such as wireless fidelity (Wi-Fi), wireless local area network (WLAN), Bluetooth, and Ethernet are associated with the air interface used for the transmission and reception of the communication data between communication terminals. The processor generates the communication data as a set of packets conforming to the various communication standards. To transmit the communication data from the communication terminal, the processor transmits the set of packets to the DAC using the interface. The DAC then transmits the set of packets to the air interface using the antenna. On the other hand, during reception of the communication data, the antenna receives the set of packets. The ADC connected to the antenna receives and forwards the set of packets to the processor. However, the processor, the interface, the ADC, the DAC, and the antenna are active not only during the transmission and reception of the communication data but also when no communication data is being transmitted and received, which results in excessive power consumption by the RFIC.
One way to overcome the excessive power usage issue is to use start of frame (SOF) and end of frame (EOF) data to indicate the start and end of transmission of the communication data. Typically, the processor includes software-implemented logic to detect the SOF and EOF data. When the software-implemented logic detects the EOF data, then the processor switches off the power supply to the interface. Thus, the interface is inactivated or idle and is said to be in an idle mode.
When the software-implemented logic detects a SOF data, then the processor switches on the power supply to the interface, activating the interface such that the interface is in an active mode. The transition of the interface between the idle and active modes reduces the power consumption of the RFIC. However, the software-implemented logic is not very fast in detecting and switching the interface mode. Hence, any communication data transmitted or received during this transition period may be lost.
One way to avoid such a delay is to include a detection system between the processor and the interface to detect the EOF and SOF data. The detection system polls the interface at regular intervals to detect the EOF and SOF data, and generates a mode select signal, based on the detection of the EOF and SOF data, and transmits the mode select signal to the processor. Consequently, the processor turns the power supply on or off based on the mode select signal. The detection system overcomes the delay introduced by the software-implemented logic and thus, avoids the loss of communication data. However, the detection system has to be constantly powered to continuously poll the interface, regardless of the mode of the interface. This again results in excessive power consumption by the RFIC.
It would be advantageous to have an RFIC that uses fewer GPIO pins and has reduced power consumption.